Error (10200): Verilog HDL Conditional Statement error at ps2_con_cmd.v(11): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct 一个进程有两个驱动信号. 错误如下: always@(posedge i_clk or negedg…
1.Warning: An incorrect timescale is selected for the Verilog Output (.VO) file of this PLL design. It's required that the timescale should be 1 ps when simulating a PLL design in a third party EDA tool. 解决办法:是因为timessale不是1ps导致的错误,原因可能是之前使用过modelSim…
