module xuanpin #(parameter N=25)(clk,clr,key_in_f,key_in_z,f_out);input clk,clr,key_in_f,key_in_z;output reg f_out;reg clk0,clk1,clk2,clk3,clk4,clk5,clk6,clk7;wire key;wire key_z;reg[8:0] cnter0;reg[3:0] cnter1,cnter2,cnter3,cnter4,cnter5,cnter6,cnte